Registers
Table of contents
 Introduction
 Serialin serialout
 Serialin parallelout
 Parallelin serialout
 Parallelin parallelout
 Applications of shift registers
Introduction
A Flipflop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, you can use a group of flipflops. Such a group of flipflops is known as a Register. The nbit register will consist of n number of flipflop(s) and it is capable of storing an nbit word.
The binarydata, in a register, can be transfered within itself from one flipflop to another. A shift register is a type of register that allows such data transfers. Shift register has 4 modes of operations.
Next, let us have a look at each register operation one by one.
Serialin serialout
Let all the flipflops be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a fourbit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF3 i.e. D3 is connected to serial data input Din. The output of FF3 i.e. Q3 is connected to the input of the next flipflop i.e. D2, and so on.
Block diagram
Operation
Before application of the clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply the LSB bit of the number to Din. So Din = D3 = 1. Now, apply the clock. On the first falling edge of the clock, the FF3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock gets triggered, FF2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative clock edge gets triggered, FF1 will be set and output will get modified to Q3 Q2 Q1 Q0 = 1110.
Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111.
Truth table
Waveforms
Serialin parallelout

In such types of operations, the data is entered serially and taken out in parallel fashion.

Data is loaded bitbybit. The output(s) are disabled as long as the data is loading.

As soon as the data loading gets completed, all the flipflops contain their required data. The output(s) are enabled so that all the loaded data is made available over all the output lines at the same time.

4 clock cycles are required to load a fourbit word. Hence the speed of operation of SIPO mode is the same as that of the SISO mode.
Block diagram
Parallelin serialout

Data bits enter in a parallel fashion.

The circuit, shown below, is a fourbit parallelin serialout register.

Output of the previous flip Flop is connected to the input of the next one via a combinational circuit.

The binary input data bits B0, B1, B2, B3 are applied through the same combinational logic circuit.

There are two modes in which this circuit can work, namely  shift mode and load mode.
Load mode
When the shift/load bar line is low (0), the AND gates 2, 4 and 6 become active, and they will pass B1, B2, B3 bits to the corresponding flipflops. On the low going edge of the clock, the binary inputs B0, B1, B2, B3 will get loaded into the corresponding flipflops. Thus, the parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gates 2, 4 and 6 become inactive. Hence, the parallel loading of the data becomes impossible. But the AND gates 1,3 and 5 become active. Therefore the shifting of data takes place from lefttoright bitbybit on the application of clock pulses. Thus, the parallelin serialout operation takes place.
Block diagram
Parallelin parallelout
Here, the 4bit binary datda inputs B0, B1, B2, B3 are applied to the data inputs D0, D1, D2, D3, respectively, of the four flipflops. When a negative edge of the clock is triggered, then the flipflops get loaded with the input binary bits simultaneously. The loaded bits appear at the output side, simultaneously, as well. Only the clock pulse is essential to load all the binary bits.
Block diagram
Applications of shift registers
Overview
Shift registers are sequential circuits used primarily used for:
 Storage of Data
 Data transfer through movement of binary data
 Data manipulation
 Counter implementation
They are called shift registers as it moves or shifts binary input data to its output per clock cycle. Shift registers are commonly used to store data inside calculators. Even in computer systems, operations like addition, subtraction, division and multiplication are performed by registers.
Shift registers can be applied in the following ways:

Parallel to Serial conversion: Used in transmitters after analog to digital conversion in order to convert parallel input data into serial data

Serial to Parallel conversion: Used in receivers before digital to anlogous conversion takes place in order to convert serial input data into parallel data

Sequence Generator: Generate a sequence of 0s and 1s when combined with some additional gates

Counters: Shift registers can be implemented as counters based on the output of the rightmost D flipflop that is connected to the serial input, namely the Ring Counter and the Johnson Ring Counter

Serialin Serialout registers are used for time delays
Ring counter
Similar to how the Serialin Serialout register requires ‘N’ clock pulses to shift N bit data, the ‘N’ Ring Counter produces a sequence of 0s and 1s, by having the rightmost D flipflop as input to the leftmost D flipflop as opposed to applying data externally. That is, the output of the last flipflop is connected to the output of the first flipflop in the ring. These patterns of states (0s and 1s) are repeated every ‘N’ clock cycles.
The number of states in a Ring Counter are directly proportional to the number of flipflops used.
The block diagram of the 3bit Ring counter is shown in the following figure.
A 3bit Ring Counter will contain only a 3bit SIPO shift register.
Assume, the initial status of the D flipflops from leftmost to rightmost is Q2Q1Q0=001. Here, Q2 & Q0 are MSB & LSB respectively. You can understand the working of Ring counter from the following table.
No of positive edge of Clock  Serial Input = Q0  Q2(MSB)  Q1  Q0(LSB) 

0    0  0  1 
1  1  1  0  0 
2  0  0  1  0 
3  0  0  0  1 
Due to the absence of the clock signal, the initial status of the D flipflops is Q2Q1Q0=001. This state will repeat every third positive edge transition of the clock signal.
Similarly, the following operations take place every positive edge of the clock cycle:

Serial input of the first D flipflop gets the previous output of the third flipflop. Thus, the present output of the first D flipflop is equal to the previous output of the third flipflop.

The previous outputs of first and second D flipflops are rightshifted by one bit. That implies that the present outputs of second and third D flipflops are equal to the previous outputs of first and second D flipflops.
Johnson ring counter
The Johnson ring counter functions similarly to the Ring counter. The difference being that the complemented output of rightmost D flipflop is given as input of leftmost D flipflop instead of normal output. Thus, ‘N’ bit Johnson Ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every ‘2N’ clock cycles.
Johnson ring counter is also called the Twisted ring counter and Switch tail ring counter. The block diagram of 3bit Johnson Ring counter is shown in the following figure.
The 3bit Johnson Ring counter also contains only a 3bit SIPO shift register.
Assume, initially, all the D flipflops are cleared. So, Q2Q1Q0=000. Here, Q2 is the MSB & Q0 is the LSB.
No of positive edge of Clock  Serial Input = Q0  Q2(MSB)  Q1  cQ0(LSB) 

0    0  0  0 
1  1  1  0  0 
2  1  1  1  0 
3  1  1  1  1 
4  0  0  1  1 
5  0  0  0  1 
6  0  0  0  0 
The initial status of the D flipflops in the absence of the clock signal is Q2Q1Q0=000. This status repeats for every six positive edge transitions of the clock signal.
Similarly, the following operations take place for every positive edge of the clock signal.
 Serial input of first D flipflop gets the previous complemented output of the third flipflop. So, the present output of the first D flipflop is equal to the previous complemented output of the third flipflop.
 The previous outputs of first and second D flipflops are right shifted by one bit. That means, the present outputs of second and third D flipflops are equal to the previous outputs of first and second D flipflops.