Master-slave JK flip-Flop
Table of contents
- Master-slave JK flip-flop constructed by using NAND gates
- State table
- Characteristic table
- Excitation table
- Characteristic equation
Master-slave JK flip-flop is designed to eliminate the race around condition in JK flip-flop and it is constructed by using two JK flip-flops as shown in the circuit diagram below.
The first flip-flop is called the master, and it is driven by the positive clock cycle. The second flip-flop is called the slave, and it is driven by the negative clock cycle. During the positive clock cycle, master flip-flop gives the intermediate output but slave flip-flop will not give the final output. During the negative clock cycle, slave flip-flop gets activated and copies the previous output of the master flip-flop and produces the final output.
Master-slave JK flip-flop constructed by using NAND gates
Here, Q(n) is the present state and Q(n+1) is the next state.
Q(n+1) = Q(n)'J + Q(n)K'