Table of contents

  1. Introduction
  2. Differences between latches and flip-flops
  3. Sub-modules


You covered about latches in the previous modules. Those are the basic building blocks of flip-flops. You can implement flip-flops in two methods.

In first method, cascade two latches in such a way that the first latch is enabled for every positive clock pulse and second latch is enabled for every negative clock pulse. So that the combination of these two latches become a flip-flop.

In second module, you can directly implement the flip-flop, which is edge sensitive. In this module, let us discuss the following flip-flops using second method.

Differences between latches and flip-flops

Latches Flip-flops
Level triggered Edge triggered
Asynchronous device Synchronous device
Doesn’t contain clock signal Contains a clock signal
It will change its state as long as it is enabled It will change its state only during a given clock cycle
Consumes less power Consumes more power
Faster Slower
Examples: D-Latch, T-Latch Examples: D-Flip flop, T-Flop flop


Now let us implement various flip-flops by providing the cross coupling between NOR gates. You can also implement these flip-flops by using NAND gates, as well.

  1. SR flip-flop
  2. D flip-flop
  3. JK flip-flop
  4. T flip-flop
  5. Master-slave JK flip-flop